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Saturday, July 11, 2009

The Introduction

Q. What are the techniques that are to be considered to increase the speed of computer?
Ans: A number of speeds – enhancing features have been incorporated into the design of computers and they are given bellow:
Cache memory: A cache is a memory unit places between the CPU and main memory M and used to store instructions, data or both. It has much smaller storage capacity than M, but it can be accessed more rapidly and is often placed on the same chip as the CPU. The cache’s effect is to reduce the average time required to access an instruction or data world, typically to just a single clock cycle. Special hardware and software techniques support the complex flow of information among M, the cache and the registers of the CPU.




Pipelined processing: pipelining allows the processing of several instructions to be partially overlapped. Pipelining is most easily done for a sequence of instructions of the same or similar types that employ a single E unit, such as a floating – point processor. All the common steps involved in instruction processing by the CPU can be pipelined:
instruction fetching (IF)
instruction decoding (ID)
operand loading (OL)
execution (EX)
operand storing (OS).
A pipelined system is often compared to an assembly line on which many products are in various stages of manufacture at the same time. In a nonpipelined CPU, instructions are executed in strict sequence. Pipelining permits the situation shown in figure where each major step of instruction processing is assigned to, handled independently by, a separate subunit of the CPU pipeline.
Superscalar processing: A microprocessors effective MIPS rate can also be increased by replicating various instructions – processing circuits so that several instructions can be in the same processing phase at the same time. This makes it possible to start the processing of two or more instruction simultaneously or in parallels. CPU with this capability are said to be superscalar. For example, if the logic needed for the IF, ID, OL, EX and OS steps is duplicated, then two instructions can be issued simultaneously.

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