Tuesday, July 14, 2009
Architecture
Monday, July 13, 2009
the third post
Q. Mention the factors that affect the performance of a computer.
Ans: The program execution time T is given by –
T=(N×CPI)/(f×〖10〗^6 ) s
here, CPI cycle per instruction
IPS instruction per second.
It is common to measure CPU performance in terms of million of instructions executed per second, denoted MIPS, where MIPS = IPS × 106. Clearly MIPS = f/CPI.
The above equation indicates the three separate factors software, architecture, and hardware technology jointly determine a computers performance.
Software: The efficiency with which the programs are written and compiled into object code influences N, the number of instructions executed. Others factors being equal, reducing n tend to reduce the overall execution time T.
Architecture: The efficiency with which individual instructions are processed directly affects CPI, the number of cycles per instruction executed. Reducing CPI also tends to reduce T.
Hardware: The raw speed of the processor circuits determines f, the clock frequency. Increasing f tends to reduce T.
Q. What do you mean by architecture and organization of computer?
Ans: Architecture: Computer architecture refers to those attributes of a system visible to a programmer or put another way, those attributes that have a direct impact on the logical execution of a program. That is, the architecture defines a conceptual model of a computer at a particular level of abstraction. The architecture includes the computer’s instruction set, data formats and addressing modes, as well as the general design of its CPU, main memory and IO subsystems.
Organization: Computer organization refers to the operational units and their interconnections that realize the architectural specifications. It refers to the logical aspects of the implementation, but the boundary between architecture and organization is vague. Organizational attributes include those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used.
Q. Briefly describe the history of computer.
Ans:
Q. Describe with figure power PC evaluation.
Ans: In the early 1990s Apple, IBM, Motorola jointly developed the power PC. It is family of single chip microprocessors, including the 601, 603 and other models, which share the common architecture derived from the POWER architecture. Used in IBM’s RISC system/600. Although it is also designated a RISC the power PC has a large number of instructions – more than 200 distinct types, in fact and its design is far from simple. It exhibits the following features that are typical of contemporary RISC – type designs:
Instructions have a fixed length and employ just a few opcode formats and addressing mode.
Only load and store instructions can access main memory.
Instruction processing is heavily pipelined.
The CPU contains several E – units.
The organization shown in figure below is a typical of the early PowerPC models, such as the 601, 603 which have three E units: an integer execution unit, a floating point unit, and a branch processing unit, allowing up to
Three instructions to be issued in the same clock cycle. The integer unit executes all fixed point numerical and logic operations, including those associated with load store instructions.
Ans: The program execution time T is given by –
T=(N×CPI)/(f×〖10〗^6 ) s
here, CPI cycle per instruction
IPS instruction per second.
It is common to measure CPU performance in terms of million of instructions executed per second, denoted MIPS, where MIPS = IPS × 106. Clearly MIPS = f/CPI.
The above equation indicates the three separate factors software, architecture, and hardware technology jointly determine a computers performance.
Software: The efficiency with which the programs are written and compiled into object code influences N, the number of instructions executed. Others factors being equal, reducing n tend to reduce the overall execution time T.
Architecture: The efficiency with which individual instructions are processed directly affects CPI, the number of cycles per instruction executed. Reducing CPI also tends to reduce T.
Hardware: The raw speed of the processor circuits determines f, the clock frequency. Increasing f tends to reduce T.
Q. What do you mean by architecture and organization of computer?
Ans: Architecture: Computer architecture refers to those attributes of a system visible to a programmer or put another way, those attributes that have a direct impact on the logical execution of a program. That is, the architecture defines a conceptual model of a computer at a particular level of abstraction. The architecture includes the computer’s instruction set, data formats and addressing modes, as well as the general design of its CPU, main memory and IO subsystems.
Organization: Computer organization refers to the operational units and their interconnections that realize the architectural specifications. It refers to the logical aspects of the implementation, but the boundary between architecture and organization is vague. Organizational attributes include those hardware details transparent to the programmer, such as control signals; interfaces between the computer and peripherals; and the memory technology used.
Q. Briefly describe the history of computer.
Ans:
Q. Describe with figure power PC evaluation.
Ans: In the early 1990s Apple, IBM, Motorola jointly developed the power PC. It is family of single chip microprocessors, including the 601, 603 and other models, which share the common architecture derived from the POWER architecture. Used in IBM’s RISC system/600. Although it is also designated a RISC the power PC has a large number of instructions – more than 200 distinct types, in fact and its design is far from simple. It exhibits the following features that are typical of contemporary RISC – type designs:
Instructions have a fixed length and employ just a few opcode formats and addressing mode.
Only load and store instructions can access main memory.
Instruction processing is heavily pipelined.
The CPU contains several E – units.
The organization shown in figure below is a typical of the early PowerPC models, such as the 601, 603 which have three E units: an integer execution unit, a floating point unit, and a branch processing unit, allowing up to
Three instructions to be issued in the same clock cycle. The integer unit executes all fixed point numerical and logic operations, including those associated with load store instructions.
Saturday, July 11, 2009
The Introduction
Q. What are the techniques that are to be considered to increase the speed of computer?
Ans: A number of speeds – enhancing features have been incorporated into the design of computers and they are given bellow:
Cache memory: A cache is a memory unit places between the CPU and main memory M and used to store instructions, data or both. It has much smaller storage capacity than M, but it can be accessed more rapidly and is often placed on the same chip as the CPU. The cache’s effect is to reduce the average time required to access an instruction or data world, typically to just a single clock cycle. Special hardware and software techniques support the complex flow of information among M, the cache and the registers of the CPU.
Pipelined processing: pipelining allows the processing of several instructions to be partially overlapped. Pipelining is most easily done for a sequence of instructions of the same or similar types that employ a single E unit, such as a floating – point processor. All the common steps involved in instruction processing by the CPU can be pipelined:
instruction fetching (IF)
instruction decoding (ID)
operand loading (OL)
execution (EX)
operand storing (OS).
A pipelined system is often compared to an assembly line on which many products are in various stages of manufacture at the same time. In a nonpipelined CPU, instructions are executed in strict sequence. Pipelining permits the situation shown in figure where each major step of instruction processing is assigned to, handled independently by, a separate subunit of the CPU pipeline.
Superscalar processing: A microprocessors effective MIPS rate can also be increased by replicating various instructions – processing circuits so that several instructions can be in the same processing phase at the same time. This makes it possible to start the processing of two or more instruction simultaneously or in parallels. CPU with this capability are said to be superscalar. For example, if the logic needed for the IF, ID, OL, EX and OS steps is duplicated, then two instructions can be issued simultaneously.
Ans: A number of speeds – enhancing features have been incorporated into the design of computers and they are given bellow:
Cache memory: A cache is a memory unit places between the CPU and main memory M and used to store instructions, data or both. It has much smaller storage capacity than M, but it can be accessed more rapidly and is often placed on the same chip as the CPU. The cache’s effect is to reduce the average time required to access an instruction or data world, typically to just a single clock cycle. Special hardware and software techniques support the complex flow of information among M, the cache and the registers of the CPU.
Pipelined processing: pipelining allows the processing of several instructions to be partially overlapped. Pipelining is most easily done for a sequence of instructions of the same or similar types that employ a single E unit, such as a floating – point processor. All the common steps involved in instruction processing by the CPU can be pipelined:
instruction fetching (IF)
instruction decoding (ID)
operand loading (OL)
execution (EX)
operand storing (OS).
A pipelined system is often compared to an assembly line on which many products are in various stages of manufacture at the same time. In a nonpipelined CPU, instructions are executed in strict sequence. Pipelining permits the situation shown in figure where each major step of instruction processing is assigned to, handled independently by, a separate subunit of the CPU pipeline.
Superscalar processing: A microprocessors effective MIPS rate can also be increased by replicating various instructions – processing circuits so that several instructions can be in the same processing phase at the same time. This makes it possible to start the processing of two or more instruction simultaneously or in parallels. CPU with this capability are said to be superscalar. For example, if the logic needed for the IF, ID, OL, EX and OS steps is duplicated, then two instructions can be issued simultaneously.
Friday, July 10, 2009
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